In computer engineering, a loadâÂÂstore architecture (or a registerâÂÂregister architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).
Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are loadâÂÂstore architectures.
For instance, in a loadâÂÂstore approach, both the operands and the destination for an ADD operation must be in registers. This differs from a registerâÂÂmemory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory while the other is in a register. The earliest example of a loadâÂÂstore architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the loadâÂÂstore approach.