In digital electronics, the powerâÂÂdelay product (PDP) is a figure of merit correlated with the energy efficiency of a logic gate or logic family. Also known as switching energy, it is the product of power consumption P (averaged over a switching event) times the inputâÂÂoutput delay or duration of the switching event D. It has the dimension of energy and measures the energy consumed per switching event.
In a CMOS circuit the switching energy and thus the PDP for a 0-to-1-to-0 computation cycle is C<sub>L</sub>÷V<sub>DD</sub><sup>2</sup>. Therefore, lowering the supply voltage V<sub>DD</sub> lowers the PDP.
Energy-efficient circuits with a low PDP may also be performing very slowly, thus energyâÂÂdelay product (EDP), the product of E and D (or P and D<sup>2</sup>), is sometimes a preferable metric.
In CMOS circuits the delay is inversely proportional to the supply voltage V<sub>DD</sub> and hence EDP is proportional to V<sub>DD</sub>. Consequently, lowering V<sub>DD</sub> also benefits EDP.