The REX prefix (from "register extensions") and REX coding scheme was introduced as part of AMD's x86-64 instruction set architecture that extended Intel's IA-32 instruction set architecture for microprocessors from Intel, AMD and others.
It provides additional space for encoding 64-bit addressing modes and additional registers present in the x86-64 architecture.
The one-byte REX prefix can be added to new and existing instructions. It provides 4 bits of payload in total and allows addressing 16 registers.
A two-byte REX2 prefix was proposed by Intel's Advanced Performance Extensions in 2023 that would offer 8 bits of payload and allow addressing 32 registers.
The REX coding scheme uses an opcode prefix consisting of one byte, which may be added to existing or new instruction codes.
It has the four high-order bits set to four, which replaces sixteen opcodes numbered 0x40âÂÂ0x4F. Previously, those opcodes were individual INC and DEC instructions for the eight standard processor registers; x86-64 code must use ModR/M INC and DEC instructions.
In the x86 architecture, instructions with a memory operand almost always use the ModR/M byte which specifies the addressing mode. This byte has three bit fields:
The base-plus-index and scale-plus-index forms of 32-bit addressing (encoded with r/m = 100 and mod â 11) require another addressing byte, the SIB byte. It has the following fields:
The REX prefix<nowiki/>'s bit-field W changes the operand size to 64 bits, R expands reg to 4 bits, B expands r/m (or opreg in the few opcodes that encode the register in the 3 lowest opcode bits, such as "POP reg"), and X and B expand index and base in the SIB byte.
The REX2 prefix is a 2-byte variant of the REX prefix, that is proposed with Intel's Advanced Performance Extensions and allows addressing 32 registers.