Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.
The following instructions were introduced in the Intel 80386, but later discontinued:
These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation.
These instructions were introduced in 6th generation Intel Core "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs.
Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds.
The <code>XSAVE</code> area that was used to save MPX registers on context switches has been repurposed for APX.
The Hardware Lock Elision feature of Intel TSX is marked in the Intel SDM as removed from 2019 onwards. This feature took the form of two instruction prefixes, <code>XACQUIRE</code> and <code>XRELEASE</code>, that could be attached to memory atomics/stores to elide the memory locking that they represent.
The <code>XACQUIRE</code> and <code>XRELEASE</code> prefixes can be used with the following instructions:
These prefixes cannot be used with the <code>CMPXCHG16B</code> instruction, nor with the direct-offset store opcodes (opcodes <code>A2h</code>/<code>A3h</code>).
The VP2INTERSECT instructions (an AVX-512 subset) were introduced in Tiger Lake (11th generation mobile Core processors), but were never officially supported on any other Intel processors â they are now considered deprecated and are listed in the Intel SDM as removed from 2023 onwards.
As of July 2024, the VP2INTERSECT instructions have been re-introduced on AMD Zen 5 processors.
The first generation Xeon Phi processors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is available â the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for the <code>KMOV</code>, <code>KNOT</code> and <code>KORTEST</code> instructions â these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names).
Most of these KNC-unique instructions are similar but not identical to instructions in AVX-512 â later Xeon Phi processors replaced these instructions with AVX-512.
Early versions of AVX-512 avoided the instruction encodings used by KNC's MVEX prefix, however with the introduction of Intel APX (Advanced Performance Extensions) in 2023, some of the old KNC MVEX instruction encodings have been reused for new APX encodings. For example, both KNC and APX accept the instruction encoding as valid, but assign different meanings to it:
Some of the AVX-512 instructions in the Xeon Phi "Knights Landing" and later models belong to the AVX-512 subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors. The ER and PF subsets were introduced in "Knights Landing" â the 4FMAPS and 4VNNIW instructions were later added in "Knights Mill".
The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where:
The AVX512PF instructions are a set of 16 prefetch instructions. These instructions all use VSIB encoding, where a memory addressing mode using the SIB byte is required, and where the index part of the SIB byte is taken to index into the AVX512 vector register file rather than the GPR register file. The selected AVX512 vector register is then interpreted as a vector of indexes, causing the standard x86 base+index+displacement address calculation to be performed for each vector lane, causing one associated memory operation (prefetches in case of the AVX512PF instructions) to be performed for each active lane. The instruction encodings all follow a pattern where:
The AVX512_4VNNIW instructions read a 128-bit data item from memory, containing 4 two-component vectors (each component being signed 16-bit). Then, for each of 4 consecutive AVX-512 registers, they will, for each 32-bit lane, interpret the lane as a two-component vector (signed 16-bit) and perform a dot-product with the corresponding two-component vector that was read from memory (the first two-component vector from memory is used for the first AVX-512 source register, and so on). These results are then accumulated into a destination vector register.
Xeon Phi processors (from Knights Landing onwards) also featured the <code>PREFETCHWT1 m8</code> instruction (opcode <code>0F 0D /2</code>, prefetch into L2 cache with intent to write) â these were the only Intel CPUs to officially support this instruction, but it continues to be supported on some non-Intel processors (e.g. Zhaoxin YongFeng).
A handful of instructions to support System Management Mode were introduced in the Am386SXLV and Am386DXLV processors. They were also present in the later Am486SXLV/DXLV and Elan SC300/310 processors.
The SMM functionality of these processors was implemented using Intel ICE microcode without a valid license, resulting in a lawsuit that AMD lost in late 1994. As a result of this loss, the ICE microcode was removed from all later AMD CPUs, and the SMM instructions removed with it.
These SMM instructions were also present on the IBM 386SLC and its derivatives (albeit with the <code>LOADALL</code>-like SMM return opcode <code>0F 07</code> named <code>ICERET</code>), as well as on the UMC U5S processor.
The 3DNow! instruction set extension was introduced in the AMD K6-2, mainly adding support for floating-point SIMD instructions using the MMX registers (two FP32 components in a 64-bit vector register). The instructions were mainly promoted by AMD, but were supported on some non-AMD CPUs as well. The processors supporting 3DNow! were:
3DNow! also introduced a couple of prefetch instructions: (opcode ) and (opcode ). These instructions, unlike the rest of 3DNow!, are not discontinued but continue to be supported on modern AMD CPUs. The <code>PREFETCHW</code> instruction is also supported on Intel CPUs starting with Pentium 4, albeit executed as NOP until Broadwell.