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SHA instruction set

A SHA instruction set is a set of extensions to the ARM, RISC-V and x86 instruction set architecture which support hardware acceleration of the Secure Hash Algorithm (SHA) family.

ARM

SHA-1 and SHA-256 instructions appeared as optional features (FEAT_SHA1 and FEAT_SHA256) in the Arm V8.0 architecture introduced in 2011. The instructions are:

  • SHA-1: <code>SHA1C</code>, <code>SHA1H</code>, <code>SHA1M</code>, <code>SHA1P</code>, <code>SHA1SU0</code>, <code>SHA1SU1</code>
  • SHA-256: <code>SHA256H</code>, <code>SHA256H2</code>, <code>SHA256SU0</code>, <code>SHA256SU1</code>

SHA-512 and SHA-3 instructions appeared as optional features (FEAT_SHA512 and FEAT_SHA3) in the Arm V8.2 architecture. The instructions are:

  • SHA-512: <code>SHA512H</code>, <code>SHA512H2</code>, <code>SHA512SU0</code>, <code>SHA512SU1</code>
  • SHA-3: <code>EOR3</code>, <code>RAX1</code>, <code>XAR</code>, <code>BCAX</code>

A scalable vector extension (SVE) version of the SHA-3 instructions appeared as an optional feature (FEAT_SVE_SHA3) in the Arm V9.0 architecture.

RISC-V

SHA2 instructions are part of the Zknh extension part of the RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions ratified in November 2021.

x86 architecture processors

The original SSE-based extensions added four instructions supporting SHA-1 and three for SHA-256 and were specified in 2013 by Intel. Instructions for SHA-512 was introduced in Arrow Lake and Lunar Lake in 2024. .

  • SHA-1: <code>SHA1RNDS4</code>, <code>SHA1NEXTE</code>, <code>SHA1MSG1</code>, <code>SHA1MSG2</code>
  • SHA-256: <code>SHA256RNDS2</code>, <code>SHA256MSG1</code>, <code>SHA256MSG2</code>

The newer SHA-512 instruction set comprises AVX-based versions of the original SHA instruction set marked with a <code>V</code> prefix and these three new AVX-based instructions for SHA-512:

  • <code>VSHA512RNDS2</code>, <code>VSHA512MSG1</code>, <code>VSHA512MSG2</code>

AMD

All recent AMD processors support the original SHA instruction set:

  • AMD Zen (2017) and later processors.

Intel

The following Intel processors support the original SHA instruction set:

  • Intel Goldmont (2016) and later Atom microarchitecture processors.
  • Intel Cannon Lake (2018/2019), Ice Lake (2019) and later processors for laptops ("mainstream mobile").
  • Intel Rocket Lake (2021) and later processors for desktop computers.

The following Intel processors will support the newer SHA-512 instruction set:

References

External links

  • Chapter 8 of