In semiconductor electronics, Dennard scaling, also known as MOSFET scaling, is a scaling law which states roughly that, as transistors get smaller, their power density stays constant, so that the power use stays in proportion with area; both voltage and current scale (downward) with length. The law, originally formulated for MOSFETs, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named.
For long MOS transistors (i.e. one side is significantly longer than the other two), with constant electric field inside the MOS, Dennard scaling gives
where parameters are scaled by a factor of .
Explanation of symbols:
In fixed voltage scaling, the supply voltage is held constant (at ~5 V) instead of scaling like . This results in different scaling exponents. The clock frequency grows faster, at instead of , but at the price of rapidly increasing power density .
Fixed voltage scaling was the common scaling regime which ended around 2005 at the "power wall", when it was too difficult to keep the chip cool. Furthermore, at constant supply voltage, the field grows like , and the off-current grows exponentially with the field, resulting in high static power consumption since the 90 nm node.
Dennard's model of MOSFET scaling implies that, with every technology generation:
Moore's law says that the number of transistors on a microchip doubles approximately every two years. Combined with Dennard scaling, this means that performance per joule grows even faster, doubling about every 18 months (1.5 years). This trend is sometimes referred to as Koomey's law. The rate of doubling was originally suggested by Koomey to be 1.57 years, but more recent estimates suggest this is slowing.
The dynamic (switching) power consumption of CMOS circuits is proportional to frequency. Historically, the transistor power reduction afforded by Dennard scaling allowed manufacturers to drastically raise clock frequencies from one generation to the next without significantly increasing overall circuit power consumption.
However, since around 2005âÂÂ2007 Dennard scaling appears to have broken down. Specifically, leakage current and threshold voltage do not scale with size, and so the power density increases with scaling. This eventually led to a power density that is too high. This is the "power wall", which caused Intel to cancel Tejas and Jayhawk in 2004. As of 2016, transistor counts in integrated circuits are still growing, but the resulting improvements in performance are more gradual than the speed-ups resulting from significant frequency increases. The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges and also causes the chip to heat up, which creates a threat of thermal runaway and therefore further increases energy costs. Since 2005, the clock frequency has stagnated at 4-6 GHz, and the power consumption per CPU at 100 W TDP.
The breakdown of Dennard scaling and resulting inability to increase clock frequencies significantly has caused most CPU manufacturers to focus on multicore processors as an alternative way to improve performance. An increased core count benefits many (though by no means all â see Amdahl's law) workloads, but the increase in active switching elements from having multiple cores still results in increased overall power consumption and thus worsens CPU power dissipation issues. The end result is that only some fraction of an integrated circuit can actually be active at any given point in time without violating power constraints. The remaining (inactive) area is referred to as dark silicon.